Users of ASICs frequently specify a design implementation which is carried out by the ASIC manufacturer. During testing of these chips by the manufacturer, increasing current levels may be applied to the chip. If sections of the chip have been programmed with a high density of current drivers, the use of increased current levels during testing may cause a glitching phenomenon, or noise, before the individual flip-flops transition to the desired state.
This glitching or noise may be coupled through ground pins or other pins on the chip and result in noise on those nearby pins. As testing of the system is accomplished by monitoring output pins based on various inputs, the noise internal to the chip may cause the ASIC to fail the test pattern or barely pass testing, indicating an internal problem when none actually exists, that is, where the observed phenomenon is merely a result of the design of the ASIC.
Previous attempts to solve this problem have been to either (1) attempt to redesign the entire chip to reduce the density of current drivers in sections of the chip, (2) alter the test vectors used during the test to exercise portions of the chip so as to avoid false transitions, or (3) test the chip on a more sophisticated and more expensive testing device, requiring more test time and man hours and lowering the number of ASICs produced in a fixed period of time.
Accordingly, a principal object of the present invention is to provide a testing method which can be performed quickly on a relatively inexpensive test station and which minimizes the effects of noise internal to the ASIC without redesigning the entire ASIC. Such a method should minimize the number of false test failure indications at a low cost in dollars and man hours.
A further object of this invention is to provide a low-cost test environment which can be used for all ASIC designs, not only those designs having no false test indications during testing.